View CS8120-D_1783615.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2001 march, 2001 rev. 7 1 publication order number: cs8120/d cs8120 5.0 v, 300 ma linear regulator with reset and enable the cs8120 is a 5.0 v, 300 ma precision linear regulator with two microprocessor compatible control functions and protection circuitry included on chip. the composite npnpnp output pass transistor assures a lower dropout voltage (1.0 v @ 200 ma) without requiring excessive supply current (2.5 ma). the cs8120's two logic control functions make this regulator well suited to applications requiring microprocessorbased control at the board or module level. enable controls the output stage. a high voltage (> 2.9 v) on the enable lead turns off the regulator's pass transistor and sends the ic into sleep mode where it draws only 250 m a. the reset function sends a reset signal when the ic is powering up or whenever the output voltage moves out of regulation. the reset signal is valid down to v out = 1.0 v. the cs8120 design optimizes supply rejection by switching the internal bandgap reference from the supply input to the regulator output as soon as the nominal output voltage is achieved. additional on chip filtering enhances rejection of high frequency transients on all external leads. the cs8120 is fault protected against short circuit, over voltage and thermal runaway conditions. features ? 5.0 v 4.0% output voltage 300 ma ? low dropout voltage (1.0 v @ 150 ma) ? low quiescent current (2.5 ma @ i out = 150 ma) ? m p compatible control functions reset enable ? low current sleep mode i q = 250 m a ? fault protection thermal shutdown short circuit 60 v load dump http://onsemi.com to220 five lead t suffix case 314d 1 5 to220 five lead tva suffix case 314k to220 five lead tha suffix case 314a 1 5 1 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information see general marking information in the device marking section on page 10 of this data sheet. device marking information d 2 pak 5pin dp suffix case 936f 1 5 so14 d suffix case 751a 1 14 dip8 n suffix case 626 1 8
cs8120 http://onsemi.com 2 pin connections so14 tab = gnd pin 1. v in 2. enable 3. gnd 4. reset 5. v out 1 to220 5 lead nc nc nc nc reset enable nc nc 114 sense nc gnd nc v out v in 1 8 gnd sense reset nc v out v in nc enable 1 pin 1. v in 2. enable 3. gnd 4. reset 5. v out dip8 d 2 pak 5pin enable + bandgap supply + gnd reset v out error amplifier figure 1. block diagram to220 v in over voltage shutdown thermal protection reset comparator + bandgap reference output current limit enable comparator to v out v ref absolute maximum ratings* rating value unit dc input voltage 0.7 to 26 v load dump 60 v output current internally limited electrostatic discharge (human body model) 2.0 kv operating temperature 40 to +125 c junction temperature 40 to +150 c storage temperature range 55 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1.) reflow (smd styles only) (note 2.) 260 peak 230 peak c c 1. 10 second maximum. 2. 60 second maximum above 183 c. *the maximum package power dissipation must be observed.
cs8120 http://onsemi.com 3 electrical characteristics (v in = 14 v, i out = 5.0 ma; 40 t j 150 c, 40 c t c 125 c, unless otherwise noted.) note 3. characteristic test conditions min typ max unit output stage output voltage, v out 7.0 v v in 26 v, 1.0 ma i out 300 ma 4.8 5.0 5.2 v line regulation 7.0 v v in 26 v, i out = 200 ma 50 mv load regulation 1.0 ma i out 300 ma 50 mv supply voltage rejection v in = 14 v dc + 1.0 v rms @ 120hz load = 25 w 40 70 db dropout voltage i out = 200 ma 1.0 1.5 v quiescent current enable = high, v in = 12 v enable = low, i out = 200 ma 0.25 2.5 0.65 15 ma ma protection circuits short circuit current 300 600 ma thermal shutdown 150 190 c overvoltage shutdown 26 40 v reset reset saturation voltage 1.0 v < v out < v rt(off) , 3.1 k w pullup to v out 0.1 0.4 v reset output leakage current enable = low, v out > v rt(on) , v reset = v out 0 25 m a power on/off reset peak output voltage 3.1 k w pullup to v out 0.7 1.0 v reset threshold high (v rh ) low (v rl) v out increasing v out decreasing 4.75 v out 0.10 v out 0.14 v out 0.04 v v reset threshold hysteresis 10 40 mv enable input high voltage 7.0 v < v in < 26 v 2.9 3.9 v input low voltage 7.0 v < v in < 26 v 1.1 2.1 v input hysteresis 7.0 v < v in < 26 v 0.4 0.8 2.8 v input current gnd < v in(hi) < v out 10 0 +10 m a 3. to have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable.
cs8120 http://onsemi.com 4 package lead description package lead # to220 5 lead dip8 so14 d 2 pak 5 pin lead symbol function 1 2 1 1 v in supply voltage to ic, usually direct from the battery. 2 4 5 2 enable cmos compatible logical input. v out is disabled i.e. placed in a high impedance state when enable is high. 3 8 13 3 gnd ground connection. 4 6 10 4 reset cmos compatible output lead. reset goes low whenever v out falls out of regulation. the reset delay is externally programmed. 5 1 14 5 v out regulated output voltage, 5.0 v (typ). n/a 7 12 sense kelvin connection which allows remote sensing of output voltage for improved regulation. if remote sensing is not de- sired, connect to v out. 3, 5 2, 3, 4, 6, 7, 8, 9, 11 nc no connection. typical performance characteristics junction temperature ( c ) 40 20 0 20 40 60 80 100 120 figure 2. output voltage vs. temperature 5.01 5.0 4.99 4.98 4.97 4.96 4.95 v out (v) 140 150 figure 3. load regulation vs. output current over temperature i out ( ma ) 0 100 200 300 400 500 0 5 10 15 20 25 50 load reg. (mv) i out = 100 ma 5.0 v @ 25 c 30 35 40 45 v in = 14 v 25 c 40 c 5.02 125 c
cs8120 http://onsemi.com 5 typical performance characteristics figure 4. line regulation vs. output current over temperature figure 5. dropout voltage vs. output current over temperature i out (ma) 0 50 100 150 200 250 300 350 400 50 40 30 20 10 0 10 line reg. (mv) 450 500 v in = 7 to 25 v 125 c 25 c 40 c output current (ma) 0 50 100 150 200 250 300 350 1.4 1.0 0.8 0.6 0.4 0.2 0.0 dropout voltage. (v) 125 c 25 c 40 c 1.2 figure 6. quiescent current vs. output current over temperature supply voltage (v) 02 46810 5.5 4 3 2 1 0 v out (v) v out i q 5 output current (ma) 0 50 100 150 200 250 3.0 2.0 1.5 1.0 0.5 0.0 quiescent current (ma) v in = 14 v 2.5 125 c 25 c 40 c 3.5 300 350 figure 7. output voltage and supply current vs. input voltage figure 8. reset output voltage vs. output voltage reset output current (ma) 1 5 10 15 20 25 1400 1000 800 600 400 0 reset output voltage (mv) 1200 30 35 40 200 0 4 8 12 16 22 20 supply current (ma) v in = 5.0 v 1600 1800 2000
cs8120 http://onsemi.com 6 circuit description voltage reference and output circuitry precision voltage reference the regulated output voltage depends on the precision band gap voltage reference in the ic. by adding an error amplifier into the feedback loop, the output voltage is maintained within 4.0% over temperature and supply variation. output stage the composite pnpnpn output structure (figure 9) provides 300 ma (typ) of output current while maintaining a low drop out voltage (1.00 v, typ) and drawing little quiescent current (2.5 ma). the npn pass device prevents deep saturation of the output stage which in turn improves the ic's efficiency by preventing excess current from being used and dissipated by the ic. figure 9. composite output stage of the cs8120 v in v out output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (figure 10). figure 10. typical circuit waveforms for output stage protection i out load dump v in v out thermal shutdown short circuit > 26 v if the input voltage rises above 26 v (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. using an emitter sense scheme, the amount of current through the npn pass transistor is monitored. feedback circuitry insures that the output current never exceeds a preset limit. should the junction temperature of the power device exceed 180 c (typ) the power transistor is turned off. thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the ic. regulator control functions the cs8120 contains two microprocessor compatible control functions: enable and reset (figure 11). enable function the enable function switches the output transistor. when the voltage on the enable lead exceeds 2.9 v typ, the output pass transistor turns off, leaving a high impedance facing the load. the ic will remain in sleep mode, drawing only 250 m a, until the voltage on the lead drops below 2.1 v typ. hysteresis (800 mv) is built into the enable function to provide good noise immunity. figure 11. circuit waveform for cs8120 (1) = no reset delay capacitor v in v out enable reset (2) = with reset delay capacitor vr lo vr peak vr peak for 7.0 v < v in < 26 v v in(h) v rh v rl (1) (2) reset function a reset signal (low voltage) is generated as the ic powers up (v out > v out 100 mv) or when v out drops out of regulation (v out < v out 140 mv, typ). 40 mv of hysteresis is included in the function to minimize oscillations. the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic, thereby
cs8120 http://onsemi.com 7 guaranteeing that the reset signal is valid for v out as low as 1.0 v. figure 12. rc network for reset delay circuitry v out cs8120 5.0 v to m p and system power reset r rst to m p reset port c rst c 2 22 m f an external rc network on the reset lead (figure 12) provides a sufficiently long delay for most microprocessor based applications. rc values can be chosen using the following formula: r tot c rst t delay ln v t v out v rst v out
where: r tot = r rst in parallel with r in , r in = m p port impedance, c rst = reset delay capacitor, t delay = desired delay time, v rst = v sat of reset lead (0.7 v @ turn on), and v t = m p logic threshold voltage. application notes the circuit depicted in figure 13 lets the microprocessor control its power source, the cs8120 regulator. an i/o port on the m p and the switch port are used to drive the base of q1. when q1 is driven into saturation, the voltage on the enable lead falls below its lower threshold. the regulator's output is switched out. when the drive current is removed, the voltage on the enable lead rises, the output is switched off and the ic moves into sleep mode where it draws 250 m a. by coupling these two controls with the enable , the system has added flexibility. once the system is running, the state of the switch is irrelevant as long as the i/o port continues to drive q1. the microprocessor can turn off its own power by withdrawing drive current, once the switch is open. this software control at the i/o port allows the microprocessor to finish key housekeeping functions before power is removed. the logic options are summarized in table 1. table 1. logic control of cs8120 output microprocessor i/o drive switch enable output on closed low on open low on off closed low on open high off the i/o port of the microprocessor typically provides 50 m a to q1. in automotive applications the switch is connected to the ignition switch. v bat switch q1 500 k w 0.1 m f 500 k w 100 k w 100 k w c rst 22 m f r rst v cc reset i/o port m p v out reset enable v in figure 13. microprocessor control of cs8120 using external switching transistor q1 cs8120 gnd c1 c2
cs8120 http://onsemi.com 8 stability considerations the output or compensation capacitor, c 2 , helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c 2 shown in figure 14 should work for most applications, however it is not necessarily the optimized solution. v in figure 14. circuit showing output compensation capacitor c 1 * 0.1 m f enable v out r rst c 2 ** 10 m f reset cs8120 *c 1 is required if regulator is far from the power source filter . **c 2 is required for stability. c rst to m p reset port 5.0 v to m p and system power to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 15) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c.
cs8120 http://onsemi.com 9 in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 15. single output regulator with key performance parameters labeled smart regulator ? control features i out i in i q v in v out heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8120 http://onsemi.com 10 ordering information device description shipping cs8120yt5 to220 five lead straight 50 units/rail cs8120ytva5 to220 five lead vertical 50 units/rail cs8120ytha5 to220 five lead horizontal 50 units/rail cs8120yn8 dip8 50 units/rail cs8120ydp5 d 2 pak, 5pin 50 units/rail cs8120ydpr5 d 2 pak, 5pin 750 tape & reel cs8120yd14 so14 55 units/rail cs8120ydr14 so14 2500 tape & reel marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week to220 five lead t suffix case 314d cs8120 awlyww 1 to220 five lead tva suffix case 314k cs8120 awlyww 1 to220 five lead tha suffix case 314a cs8120 awlyww 1 1 8 cs8120 awl yyww dip8 n suffix case 626 cs8120 awlyww 1 d 2 pak 5pin dp suffix case 936f so14 d suffix case 751a 1 cs8120 awlyww 14
cs8120 http://onsemi.com 11 package dimensions to220 five lead t suffix case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to220 five lead tva suffix case 314k01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t s l 12345 seating plane r m w
cs8120 http://onsemi.com 12 to220 five lead tha suffix case 314a03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 t seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q p t dim min max min max millimeters inches a 0.326 0.336 8.28 8.53 b 0.396 0.406 10.05 10.31 c 0.170 0.180 4.31 4.57 d 0.026 0.035 0.66 0.91 e 0.045 0.055 1.14 1.40 f 0.090 0.110 2.29 2.79 g 0.067 bsc 1.70 bsc h 0.098 0.108 2.49 2.74 j 0.018 0.025 0.46 0.64 k 0.204 0.214 5.18 5.44 m 0.055 0.066 1.40 1.68 n 0.000 0.004 0.00 0.10 b a k m e c seating plane f h j d 5 pl g t m 0.13 (0.005) m b 12345 d 2 pak 5pin dp suffix case 936f01 issue o
cs8120 http://onsemi.com 13 so14 d suffix case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 dip8 n suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 package thermal data parameter to220 five lead d 2 pak five lead dip8 so14 unit r q jc typical 3.1 3.1 52 30 c/w r q ja typical 50 1050* 100 125 c/w * depending on thermal properties of substrate. r q ja = r q jc + r q ca
cs8120 http://onsemi.com 14 notes
cs8120 http://onsemi.com 15 notes
cs8120 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8120/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

▲Up To Search▲

Price & Availability of CS8120-D

	To Download CS8120-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .